1. Field of the Invention
This specification relates to an organic light emitting display, and more particularly, an organic light emitting display capable of preventing brightness reduction by compensating for degradation of a device due to change of a threshold voltage, and a driving method thereof.
2. Background of the Invention
As information society develops, demands for display devices for displaying images increase in various manners. Recently, various flat display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diodes (OLEDs) are being utilized.
Among such flat display devices, the OLEDs have advantages such as a low voltage driving, a thin thickness, an excellent viewing angle, and a fast response speed. As the OLEDs, active matrix type OLEDs for displaying images as pixels are arranged in the form of matrices are being widely used.
FIG. 1 is a view illustrating a configuration of an organic light emitting display in accordance with the related art, and FIG. 2 is an equivalent circuit diagram with respect to a single pixel of FIG. 1.
Referring to the drawings, the related art organic light emitting display 1 includes a display panel 2, a timing controller 3, a driving voltage generator 4, a gate driving unit 5, and a data driving unit 6.
The display panel 2 is configured to display images, and a plurality of gate lines (GL1˜GLn) and a plurality of data lines (DL1˜DLm) for defining pixel regions by crossing each other are formed at the display panel 2.
As shown in FIG. 2, a pixel (P) is formed at each pixel region. The pixel (P) includes a switching transistor (ST), a capacitor (C), a driving transistor (DR) and an organic light emitting diode (OLED) each formed between a gate line (GL1) and a data line (DL1). Each transistor (ST, DR) is a thin film transistor (TFT) formed of amorphous silicon (a-Si:H).
The switching transistor (ST) of the pixel (P) may have a gate electrode connected to a gate line (GL1), a source electrode connected to a data line (DL1), and a drain electrode connected to a gate electrode of the driving transistor (DR). The switching transistor (ST) supplies a data signal supplied to the data line (DL1) to the driving transistor (DR), according to a gate signal supplied to the gate line (GL1).
Further, the driving transistor (DR) may have a gate electrode connected to the drain electrode of the switching transistor (ST), a source electrode connected to the OLED, and a drain electrode connected to a line for supplying a power voltage (VDD). The driving transistor (DR) controls the amount of current flowing to the OLED from the power voltage (VDD), according to a data signal supplied from the switching transistor (ST).
The capacitor (C) is connected between the gate electrode of the driving transistor (DR) and the OLED. The capacitor (C) stores therein a voltage corresponding to a data signal supplied to the gate electrode of the driving transistor (DR), and constantly maintains an ‘ON’ state of the driving transistor (DR) for a single frame using the stored voltage.
The timing controller 3 generates image data (R′, G′, B′) by converting image signals (R, G, B) provided from the outside, and outputs the generated image data to the data driving unit 6.
The timing controller 3 generates gate control signals (CNT1) and data control signals (CNT2) from a control signal (CTN) provided from the outside, and outputs the generated signals to the gate driving unit 5 and the data driving unit 6, respectively.
The data driving unit 6 is connected to the plurality of data lines (DL1˜DLm) of the display panel 2, and generates data signals using the data control signals (CNT2) and the image data (R′, G′, B′) received from the timing controller 3. The data signals are supplied to the plurality of data lines (DL1˜DLm) of the display panel 2.
The driving voltage generator 4 generates a gate high voltage (Vgh) and a gate low voltage (Vgl), and outputs the generated voltages to the gate driving unit 5.
The gate driving unit 5 is connected to the plurality of gate lines (GL1˜GLn) of the display panel 2, and generates gate signals using the signals provided from the driving voltage generator 4 (i.e., the gate high voltage (Vgh) and the gate low voltage (Vgl)), according to the gate control signals (CNT1) received from the timing controller 3. The gate signals are supplied to the plurality of gate lines (GL1˜GLn) of the display panel 2.
In the related art organic light emitting display 1, the switching device of the pixel (P), i.e., the switching transistor (ST) and the driving transistor (DR) are degraded as time lapses, and thus a threshold voltage (Vth) of the switching device is changed.
FIG. 3 is a graph illustrating a brightness change according to a threshold voltage change, in the related art organic light emitting display.
Referring to FIG. 3, in the related art organic light emitting display 1, a threshold voltage (Vth) of a switching device of a pixel (P) is gradually increased as time lapses.
As the threshold voltage (Vth) is increased, a non-uniform amount of current flows to the OLED, even if a data signal of the same level is applied to the switching device (i.e., the switching transistor ST). As a result, brightness of the display panel 2 is gradually reduced as time lapses. This may lower a lifespan of the organic light emitting display 1.